Synthesis results from a modified, defect aware, Verilog-To-Routing synthesis flow. These result files were derived from the MCNC20 benchmarks synthesized on various memristor-based FPGA architecture configurations for different error patterns and error rates. A basic description of the structure of the data is provided in the included README file.

This dataset is used to derive the conclusions and figures for the related journal submission. Further inquiries about this data, the processing or implementation methods can be made to the corresponding author of the article.

Due to the large number of small files contained in this dataset, it is provided as ZIP archive.