The goal of these joint VESUVIO/ChipIR proposed experiments is to characterize the SEU occurrence on new generation FPGA caused by neutrons. We will focus on a Commercial Off-The-Shelf (COTS) component, in order to evaluate its robustness and its potential use in space environment in particular for micro and nano satellites. Due to their weight, power and budget limitations, and their low altitude operation, these satellites commonly use high performance COTS components.FPGAs represent a very interesting solution for signal acquisition, processing and transmission in such satellites. In this frame, their susceptibility to neutrons is an fundamental issue. The main purpose of the experiment is to make an accurate diagnosis of what are the faults produced in very high density FPGA. This analysis could lead to the creation of a reliability model of the FPGA.