Semiconductor industry is currently offering 7 nm technology node with FinFET fabrication processes. Soft error causing mechanisms and error rates for FinFET technologies are expected to be vastly different from those for older planar technologies. This proposal is for the investigation of muon-induced soft errors for 7 nm SRAM and flip-flop (FF) designs. We will be using standard SRAM designs and a custom-designed test IC containing multiple hardened and non-hardened FF and logic circuit designs. Since soft errors caused by muons may be significantly higher than that observed for prior technologies, tests are needed to understand their effects and failure rates to allow for development of predictive models. Results from these experiments will be supported with circuit simulations. Results will support a dissertation and will be disseminated through publications.