Dataset containing monitoring of various hardware performance counters (HPCs) and executed instructions associated with the proof-of-concept of 16 side-channel attacks (access-retired, evict-reload, fence-flush, flush-fault, flush-fault-ret, flush-flush, flush-reload, ghostwrite, iflush-reload, interrupt-timing, page-walk, spectre-rsb, spectre-v1, spectre-v2, timer-drift, tlb-evict). Some attacks were modified so that the attack occurs more frequently to obtain a larger number of samples, together with the data collected for 16 benign programs/benchmarks (bitcoin, bubble-sort, bzip2, coremark, dhrystone, ffmpeg, mandelbrot, matrix, mybench, polybench, sha256sum, sieve, speedtest, stream, stress_c, stress_m). All programs are run on a RISC-V architecture — specifically, a single-core processor is modeled using gem5’s O3 CPU to simulate realistic speculative execution, using the RISC-V ISA at 3 GHz, with a memory hierarchy that includes 16 KiB L1 caches, a unified 256 KiB L2 cache, and 4 GiB DDR4-2400 memory, recording statistics every 10,000 instructions for detailed performance analysis.

The selection of the hardware attacks used to collect the data was made based on the benchmark set employed in the physical-hardware tests to verify whether the simulation produced results faithful to those obtained when running the exploits on a physical board. Concretely, we relied on the dataset "RISC-V hardware attack traces on on-chip hardware performance counters (HARPY-V Dataset)", https://doi.org/10.34810/data2538.

The selection of benign programs was primarily based on benchmark suites that offered reliable and reproducible execution behavior, thus enabling effective comparison with the workloads. A range of different benchmark suites with varied approaches was chosen to ensure optimal coverage of the dataset.